1. Field of the Invention
The present invention pertains to a method of micromachining a multi-part cavity in a substrate, wherein different parts of the cavity may be formed to have different shapes. The present invention also pertains to a method of forming a multi-part cavity in a semiconductor substrate, for the purpose of manufacturing a semiconductor device.
2. Brief Description of the Background Art
Numerous methods for preparing semiconductor devices which include a trench in a silicon crystal silicon or polycrystalline silicon substrate have been described in the art. A few of these methods are described below.
U.S. Pat. Nos. 4,895,810 and 5,182,234, issued Jan. 23, 1990 and Jan. 26, 1993, respectively, to Meyer and Hollinger et al., disclose methods for creating a device structure where a trench is formed in an upper silicon surface and a source conductive layer is deposited to electrically contact a source region while a gate conductive layer is deposited atop a gate oxide layer.
U.S. Pat. No. 5,229,315, issued Jul. 20, 1993 to Jun et al., discloses a method for forming an isolated film on a semiconductor device comprising the steps of: forming a deep and narrow cylindrical groove in a substrate; filling up the groove with an oxide film, and oxidizing a polysilicon layer encircled by the groove, thereby forming an isolated film in the shape of a cylinder.
U.S. Pat. No. 5,318,665, issued Jun. 7, 1994 to Oikawa, discloses a reactive ion etch method which uses a mixed gas of HBr and Ar (10 to 25%) or a mixed gas of HBr, Ar (5 to 25%) and O2 (0.2 to 2%) in etching a polysilicon film having a large step difference.
U.S. Pat. No. 5,656,535, issued Aug. 12, 1997 to Ho et al, discloses a simplified method of fabricating a storage node for a deep trench-based DRAM on a semiconductor substrate. The method involves etching a trench in a surface of the substrate and then forming a layer of dielectric material on a sidewall of the trench, the top portion of which is subsequently removed from the sidewall. Next, a layer of oxide is grown on the exposed portion of the sidewall. A portion of this layer of oxide is then removed from the sidewall in order to orient the layer of oxide a predetermined distance from the surface of the substrate. Finally, the trench is filled with a semiconductive material. The disclosure of this patent is hereby incorporated by reference herein in its entirety.
European Patent Publication Nos. 0272143 and 0565212, published Jun. 22, 1988 and Oct. 13, 1993, and assigned to the assignee of the present invention, disclose a process for etching single crystal silicon, polysilicon, silicide and polycide using iodinate or brominate gas chemistry. The disclosure of these patent publications are hereby incorporated by reference herein in their entireties.
European Patent Publication No. 0821409, published Jan. 28, 1998, by Coronel et al., discloses a collar etch method for a DRAM cell. In the manufacture of 16 Mbits DRAM chips, a polysilicon strap is used to provide an electrical contact between the drain region of the active NFET device and one electrode of the storage capacitor for each memory cell. In a conventional fabrication process, a Si3N4 pad layer is deposited onto the bare silicon substrate, then patterned. Next, deep trenches are formed in the substrate by dry etching. An ONO layer is conformally deposited into the trenches. The trenches are filled with undoped polysilicon. About 2.5 xcexcm of undoped polysilicon is removed from the trench in a plasma etcher. A TEOS SiO2 collar layer is conformally deposited, then anisotropically dry etched to leave only the so-called collar. Because trenches are present at the substrate surface, the thickness of the TEOS SiO2 collar is not uniform. The above-referenced patent publication proposes a highly selective dry etch method to anisotropically etch the TEOS SiO2 collar while preserving the Si3N4 pad layer thickness uniformity. A chemistry having a high TEOS SiO2/Si3N4 selectivity (i.e., which etches TEOS SiO2 faster than Si3N4 by a factor of at least six) is used to etch the TEOS SiO2 collar layer. C4F8/Ar and C4F8/Ar/CO mixtures which have respective selectivities approximately equal to 9:1 and 15:1 (depending on gas ratios) are said to be adequate in all respects. When the surface of the Si3N4 pad layer is reached (this can be accurately detected), the etch is continued by an overetch of the TEOS SiO2 layer to ensure a complete removal of the horizontal portions thereof. The disclosure of this patent publication is hereby incorporated by reference herein in its entirety.
European Patent Publication No. 0822593, published Feb. 4, 1998, by Haue et al., discloses a method of forming field effect transistors (FETs) on a silicon wafer. First, trenches are formed in a surface of the silicon wafer. An ONO layer is formed on the surface, lining the trenches. Potassium is diffused along the ONO layer. Part of the ONO layer is removed to expose the wafer surface with the ONO layer remaining in the trenches. Gate oxide is formed on the exposed wafer surface. Finally, FET gates are formed on the gate oxide.
Masasaki Sato et al. (Jap. J Appl. Phys., Vol. 30, No. 7, pp. 1549-1555, April 1991) disclose the effect of gas species on the depth reduction in silicon deep submicron trench reactive ion etching. In silicon deep submicron trench reactive ion etching, a clearly larger microloading effect is found in fluorinated gas than in chlorinated gas. It was noted that adoption of a heavier halogen for the etching gas offers one way to eliminate the microloading effect because ion-assisted etching is dominant in heavier halogen etching.
Geun-Young Yeom et al. (J. Electrochem. Soc., Vol. 139, No. 2, pp. 575-579, February 1992) disclose a polysilicon etchback plasma process using HBr, Cl2, and SF6 gas mixtures for deep trench isolation. A controllable trench polysilicon etchback profile with smooth surface and curvature was obtained by using 60 sccm HBr and 50 sccm Cl2 gas mixture with 6 sccm SF6 gas flow.
Commonly assigned, copending U.S. application Ser. No. 09/144,008, filed Aug. 31, 1998, by Lill et al., discloses a process for controlling the shape of the etch front in polysilicon etching applications, and a method for performing recess etchback of a polysilicon-filled trench formed in a substrate. Also disclosed is a method for forming a polysilicon-filled trench capacitor in a single-crystal silicon substrate, the trench capacitor including a dielectric collar and a buried strap. The method comprises a series of steps in which a semiconductor structure having an initial trench therein is the starting substrate.
The trench structure includes a single-crystal silicon substrate, at least one gate dielectric layer overlying a surface of the substrate, and at least one etch barrier layer overlying the gate dielectric layer. In the first step of the method, a conformal dielectric film is formed over the etch barrier layer and the sidewall and bottom of the trench. A layer of polysilicon is then applied to fill the trench. The polysilicon is then isotropically etched back to a predetermined depth within the trench using a plasma produced from a plasma source gas comprising a reactive species which selectively etches polysilicon. The plasma source gas comprises from about 80% to about 95% by volume of a fluorine-comprising gas, and from about 5% to about 20% by volume of an additive gas selected from a group consisting of a bromine-comprising gas, a chlorine-comprising gas, an iodine-comprising gas, or a combination thereof. After the polysilicon etchback, a collar is formed by application of a conformal layer of silicon oxide over the etch barrier layer, the sidewall of the trench, and the portion of the polysilicon which was exposed during the etching step. The silicon oxide collar is then anisotropically etched back to a first depth to expose the underlying polysilicon. The trench is then refilled with polysilicon. The polysilicon is subsequently etched back to a second predetermined depth within the trench using a plasma produced from a plasma source gas comprising a reactive species which selectively etches polysilicon. The plasma source gas comprises from about 80% to about 95% by volume of a fluorine-comprising gas, and from about 5% to about 20% by volume of an additive gas selected from a group consisting of a bromine-comprising gas, a chlorine-comprising gas, an iodine-comprising gas, or a combination thereof.
A wet etch step is then performed to remove an upper portion of the silicon oxide collar to a third predetermined depth. The trench is then refilled with polysilicon. The polysilicon is etched back to a fourth predetermined depth within the trench, while a portion of the single-crystal silicon substrate is simultaneously removed from the top portion of the sidewall above the silicon oxide collar, thereby forming a buried strap. Preferably, polysilicon containing a dopant such as arsenic is used for at least the last polysilicon fill step, in order to facilitate electron transfer through the buried strap. The disclosure of the above patent application is hereby incorporated by reference in its entirety.
While fully effective, the method disclosed by Lill et al. includes three separate polysilicon fill and etch steps and, as such, is time-consuming. It would therefore be highly desirable to develop a quicker, more streamlined method which would result in the production of an equivalent semiconductor structure.
While attempting to simplify the production method described by Lill et al., we discovered a general method for forming a multi-part cavity in a substrate which is useful in many different micromachining applications. The general method of the invention can be applied to any application where it is necessary or desirable to provide a structure having a shaped opening and at least one underlying shaped cavity, where it is necessary to maintain tight control over the dimensions of the shaped opening. There may be several different opening shapes and different cavity shapes within one etched structure. For example, the method of the invention can be used for micromachining of test chips for performance of various chemical or biological assays (e.g., genome testing), wherein the testing reagents would be contained in a plurality of shaped cavities etched in the chip. The method of the invention can also be used for micromachining of electrostatically controlled nozzles for use in inkjet printers, wherein the ink would be contained in the shaped cavity and the shaped opening would function as a nozzle. The method of the invention allows for excellent control over the critical dimensions of the shaped opening(s) (e.g., the diameter of the nozzle), providing for consistent and reproducible micromachining of a variety of devices. Adapting the general method of the invention disclosed herein for use in a particular application can easily be done by one skilled in the art with minimal experimentation.
In accordance with the general method of the invention, a substrate is etched to a first predetermined depth to form a shaped opening. A conformal protective layer is then formed on at least the sidewall of the shaped opening. The protective layer comprises a material which has a different etch selectivity than the substrate material. If necessary, the protective layer is then anisotropically etched to remove portions of the protective layer which overlie the bottom of the shaped opening. Preferably, at least a portion of the substrate at the bottom of the shaped opening is exposed prior to proceeding with subsequent etching. The substrate is then further etched to a second predetermined depth to form a shaped cavity using an etchant gas which selectively etches the substrate relative to the protective layer.
One embodiment of the method of the invention is useful in semiconductor damascene processes and for etching trenches with embedded vessels, for example. Liquids can be guided along the trenches into the vessels. This embodiment of the invention makes use of a patterned etch barrier layer to guide the etching process. According to this embodiment, a patterned etch barrier layer is provided on an upper surface of a substrate. A portion of the upper substrate surface is exposed through the etch barrier layer. A layer of a fill material is then deposited over the etch barrier layer and the exposed upper substrate surface. A patterned masking layer is then provided on an upper surface of the fill material. A portion of the upper fill material surface is exposed through the masking layer. The fill material is then etched to a first predetermined depth to form a shaped opening. Etching is performed using an etchant gas which selectively etches the fill material relative to the etch barrier layer. This etching step exposes a sidewall of the fill material, an upper surface of the etch barrier layer, and a portion of an upper surface of the underlying substrate. A conformal protective layer is then formed over at least the sidewall of the shaped opening. The protective layer comprises a material having a different etch selectivity than the substrate and the fill material. If necessary, the protective layer is then anisotropically etched to remove portions of the protective layer which overlie the upper etch barrier layer surface and the upper substrate surface, exposing a portion of the upper substrate surface. The underlying substrate is then etched to a second predetermined depth to form a shaped cavity underlying the shaped opening, using an etchant gas which selectively etches the substrate relative to the protective layer and the etch barrier layer.
A second embodiment of the method of the invention is useful in the manufacture of vertical transistors, for example. This embodiment of the invention makes use of implanted etch stops to guide the etching process. According to this preferred embodiment, a single-crystal silicon substrate is provided. The single-crystal silicon substrate includes an implant of a material selected from the group consisting of an oxygen-comprising compound and a nitrogen-comprising compound, present at a first predetermined depth. A patterned masking layer is provided on an upper surface of the substrate. The masking layer is patterned such that the masking layer is aligned with the implanted material. A portion of the upper substrate surface is exposed through the masking layer. The substrate is then etched to a second predetermined depth to form a shaped opening using an etchant gas which selectively etches the substrate relative to the masking layer and the implanted material. The shaped opening is etched through areas of the substrate adjacent the implanted material, so that the bottom of the shaped opening is essentially coplanar with the bottom surface of the implanted material. A sidewall of the substrate and a sidewall of the implanted material are exposed during this etching step. A conformal protective layer is then formed overlying at least the exposed substrate sidewall and the exposed implanted material sidewall. The conformal protective layer comprises a material having a different etch selectivity than the substrate. If necessary, the protective layer is then anisotropically etched to remove portions of the protective layer which overlie the upper substrate surface. At least a portion of the upper substrate surface is exposed during this etching step. The underlying substrate is then etched to a third predetermined depth to form a shaped cavity, using an etchant gas which selectively etches the substrate relative to the protective layer.
A third embodiment of the method of the invention results in the formation of a double spherical profile useful as a cantilever for an accelerometer, for example. This embodiment of the invention makes use of a lateral (unpatterned) etch barrier layer to guide the etching process. According to this preferred embodiment, a film stack comprising, from top to bottom, a layer of a fill material and an etch barrier layer, is provided on an upper surface of a substrate. The fill material is then etched to a first predetermined depth to form a shaped opening. A conformal protective layer is then formed overlying at least the sidewall of the shaped opening. The conformal protective layer comprises a material having a different etch selectivity than the fill material. If necessary, the protective layer is then etched to remove portions of the protective layer which overlie the bottom of the shaped opening. At least a portion of the underlying fill material at the bottom of the opening is exposed. The underlying fill material is then isotropically etched to a second predetermined depth to form a shaped cavity, using an etchant gas which selectively etches the fill material relative to the protective layer and the etch barrier layer. An upper surface of the etch barrier layer is exposed.
An fourth, alternative embodiment of the third embodiment described above makes use of multiple lateral etch barrier layers to guide the etching process. According to this embodiment, a film stack comprising, from top to bottom, a first layer of a fill material, a first etch barrier layer, a second layer of a fill material, and a second etch barrier layer, is provided on an upper surface of a substrate. The first fill material is then etched to a first predetermined depth to form a shaped opening. Etching is performed using an etchant gas which selectively etches the first fill material relative to the first etch barrier layer. An upper surface of the first etch barrier layer is exposed during this etching step. A conformal protective layer is then formed on at least the sidewall of said shaped opening. The protective layer comprises a material having a different etch selectivity than the first fill material and the second fill material. The first etch barrier layer is then anisotropically etched to remove the portion of the first etch barrier layer at the bottom of the shaped opening. If necessary, portions of the protective layer overlying the first etch barrier layer at the bottom of the shaped opening are also removed during this etching step. At least a portion of the underlying second fill material is exposed. The underlying second fill material is then isotropically etched to a second predetermined depth to form a shaped cavity, using an etchant gas which selectively etches the second fill material relative to the protective layer and the second etch barrier layer. An upper surface of the second etch barrier layer is exposed.
As discussed above, the method of the invention is useful in many different applications. One such application is the manufacture of semiconductor devices having small feature sizes. A multi-part cavity may be formed in a substrate as a part of a semiconductor device. In one preferred embodiment, a patterned film stack comprising, from top to bottom, at least one masking layer, at least one etch barrier layer, and at least one gate dielectric layer, is provided on an upper surface of a semiconductor substrate. A portion of the upper substrate surface is exposed through the masking layer, the etch barrier layer, and the gate dielectric layer. The substrate is etched to a first predetermined depth to form a shaped opening. A conformal protective layer is then formed overlying at least the sidewall of the shaped opening. The protective layer comprises a material having a different etch selectivity than the substrate. If necessary, the protective layer is then anisotropically etched to remove portions of the protective layer which overlie the masking layer and the bottom of the shaped opening. At least a portion of the underlying substrate at the bottom of the shaped opening is exposed. The underlying substrate is then etched to a second predetermined depth to form a shaped cavity, using an etchant gas which selectively etches the substrate relative to the protective layer.
In another embodiment of the above method of the invention, a patterned film stack comprising, from top to bottom, at least one silicon oxide masking layer, at least one silicon nitride etch barrier layer, and at least one silicon oxide gate dielectric layer, is provided on an upper surface of a semiconductor substrate. The underlying substrate is then anisotropically etched to a first predetermined depth to form a shaped opening in the substrate. A conformal protective layer is then formed overlying at least the sidewall of the shaped opening. The protective layer comprises a material having a different etch selectivity than the substrate. The protective layer is then anisotropically etched to remove the portions of the protective layer which overlie the masking layer and the bottom of the shaped opening. At least a portion of the underlying substrate at the bottom of the shaped opening is exposed during this etching step. The underlying substrate is then etched to a second predetermined depth to form a shaped cavity using an etchant gas which selectively etches the substrate relative to the protective layer.
One embodiment of the above method provides an improvement over the known art pertaining to forming a trench capacitor in a single-crystal silicon substrate. According to this embodiment, a patterned film stack comprising, from top to bottom, at least one silicon oxide masking layer, at least one silicon nitride etch barrier layer, and at least one silicon oxide gate dielectric layer is provided on an upper surface of a single-crystal silicon substrate. A sidewall of the etch barrier layer, a sidewall of the gate dielectric layer, and a portion of the upper substrate surface are exposed through the masking layer, the etch barrier layer, and the gate dielectric layer. The single-crystal silicon substrate is then etched to a first predetermined depth to form a shaped opening. A conformal protective layer comprising silicon oxide is then formed overlying at least the sidewall of the shaped opening. If necessary, the protective layer is then anisotropically etched to remove portions of the protective layer which overlie the masking layer and the bottom of the shaped opening. At least a portion of the underlying single-crystal silicon substrate at the bottom of the shaped opening is exposed during this etching step. The underlying single-crystal silicon substrate is then etched to a second predetermined depth to form a shaped cavity using an etchant gas which selectively etches the single-crystal silicon substrate relative to the protective layer. A conformal dielectric film is then formed overlying the remaining masking layer, the protective layer, and the sidewalls and bottom of the shaped cavity. The shaped cavity and the shaped opening are then filled with polysilicon. The polysilicon is then isotropically etched back to a third predetermined depth within the shaped opening. A wet etch step is then performed to remove the remaining masking layer, the upper part of the conformal dielectric film, and the upper part of the protective layer to a fourth predetermined depth. The shaped opening is then refilled with polysilicon, then isotropically etched to remove the polysilicon to a fifth predetermined depth within the shaped opening. In this etching step, a portion of the single-crystal silicon substrate is also removed from the top portion of the sidewall of the shaped opening above the protective layer, to form a buried strap.
In each of the embodiments described above, the shaped cavity directly underlies and is in continuous communication with the shaped opening, and the protective layer effectively preserves the profile of the shaped opening during etching of the shaped cavity.
In U.S. application Ser. No. 09/144,088 of Lill et al., a trench capacitor is etched in a single-crystal silicon substrate to meet specifications dictated by the electrical requirements of the device being fabricated. The method of the present invention provides an alternative method for device fabrication having fewer steps than disclosed in the Lill et al. application.
Also disclosed herein is a method of protecting a silicon nitride etch barrier layer and an exposed upper sidewall of a single-crystal silicon substrate during etching. According to this method, at least one silicon nitride etch barrier is provided on an upper surface of single-crystal silicon substrate. The silicon nitride etch barrier layer has been patterned, exposing a sidewall of the silicon nitride etch barrier layer and a portion of the upper sidewall of the substrate. The exposed silicon nitride sidewall and exposed upper substrate sidewall are then oxidized, forming a thin oxidized coating over the exposed silicon nitride sidewall and upper substrate sidewall.